MUMBAI, India, June 24 -- Intellectual Property India has published a patent application (202617062743 A) filed by International Business Machines Corporation on May 18, 2026, for Stacked Fet With Asymmetric Cell Boundary.
Inventors include Xie, Ruilong; Choi, Kisik; Reboh, Shay; Clevenger, Lawrence; Alfred; Anderson, Brent, Alan; Chu, Albert, Manhee; Lanzillo, Nicholas, Anthony; and Vega, Reinaldo.
The application for the patent was published on June 12, 2026, under issue no. 24/2026.
Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.
Disclaimer: Curated by HT Syndication.
