MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202647086048 A) filed by Qualcomm Incorporated on July 14, 2026, for Stacked Memory Physical Layer (phy) Floorplan.
Inventors include Thiruvengadam, Srivatsan; and Mohan, Vivek.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: A die (110) includes a first set of physical layer (PHY) blocks arranged in a first column (512), wherein the first column (512) extends along a side (510) of the die. The die also includes a second set of PHY blocks arranged in a second column (514) adjacent to the first column (512). The first set of PHY blocks include a first PHY block, the second set of PHY blocks include a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.
Disclaimer: Curated by HT Syndication.
