MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202641087874 A) filed by Vellore Institute Of Technology on July 17, 2026, for Static Verification Of Quantum Circuits Using Pushdown Automaton.
Inventors include Rajkumar S; and G A Roopesh.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: WE CLAIM: 1. A method for static verification of a quantum circuit prior to execution on a quantum processor (100), the method comprising: receiving, by an input receiver (110), quantum circuit logic representing the quantum circuit; encoding, by a lexical encoder (120), the quantum circuit logic into a plurality of terminal tokens according to a context-free grammar; processing, by a pushdown automaton engine (130), the plurality of terminal tokens, wherein the pushdown automaton engine (130) comprises a state memory stack (132) and a qubit registry (134), and wherein processing the plurality of terminal tokens comprises: for each terminal token of the plurality of terminal tokens, performing a lookup against the state memory stack (132) to determine a current lifecycle state of a qubit associated with the terminal token; determining, based on the current lifecycle state and a grammar rule of the context-free grammar, whether a state transition indicated by the terminal token is valid; and responsive to the state transition being valid, updating the current lifecycle state of the qubit on the state memory stack (132); and generating, by an output validator (140), a verification result indicating whether the quantum circuit passes or fails verification based on the processing by the pushdown automaton engine (130). 2. The method of claim 1, wherein the current lifecycle state of the qubit comprises one of an initialized state, a superposition state, or a measured state, and wherein the pushdown automaton engine (130) transitions the qubit through the initialized state, the superposition state, and the measured state in accordance with the grammar rule. 3. The method of claim 2, wherein the state transition indicated by the terminal token is determined to be invalid when the terminal token corresponds to a quantum gate operation applied to a qubit having the measured state as the current lifecycle state. 4. The method of claim 1, wherein generating the verification result comprises: responsive to determining that the state transition indicated by the terminal token is invalid, halting verification and generating a trace-route error identifying a gate operation, a qubit identifier, and a grammar rule that was violated. 5. The method of claim 1, wherein encoding the quantum circuit logic into the plurality of terminal tokens comprises mapping hardware assembly instructions from an intermediate representation of the quantum circuit to the context-free grammar to remove framework-specific syntax. 6. The method of claim 5, wherein the intermediate representation comprises an OpenQASM representation. 7. The method of claim 1, wherein performing the lookup against the state memory stack (132) is performed in constant time complexity. 8. The method of claim 1, wherein the qubit registry (134) tracks a plurality of qubit identifiers associated with the quantum circuit, and wherein the state memory stack (132) maintains an independent lifecycle state for each qubit identifier of the plurality of qubit identifiers. 9. The method of claim 2, wherein a single-qubit gate operation transitions the qubit from the initialized state to the superposition state, a multi-qubit entanglement gate operation maintains the qubit in the superposition state, and a measurement operation transitions the qubit from the superposition state to the measured state. 10. The method of claim 1, wherein the quantum circuit logic is received in at least one of a Python abstract syntax tree format or an OpenQASM text format.
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