MUMBAI, India, Oct. 12 -- Intellectual Property India has published a patent application (202511023616 A) filed by Indian Institute Of Technology Delhi on March 17, 2025, for Stepped Pressure Ito Sputtering Method For Silicon Devices With Reduced Plasma-Induced Damage.
Inventors include Komarala Vamsi Krishna; Alam, Shahnawaz; Bhattacharya, Shrestha; Manna, Silajit; Pandey, Ashutosh; and Singh, Son Pal.
The application for the patent was published on October 09, 2026, under issue no. 41/2026.
Abstract: The present disclosure relates to a method (100) method of sputtering indium tin oxide (ITO) layers on a silicon wafer. The method includes the steps of depositing symmetrically (102) a thin layer of hydrogenated intrinsic amorphous silicon on both sides of a silicon wafer using a plasma-enhanced chemical vapor deposition (PECVD) tool. Further, the method includes depositing (104) a P-type amorphous silicon layer at a front side of the silicon wafer and a N-type amorphous silicon layer at a rear side of the silicon wafer. Additionally, four stepped indium tin oxide (ITO) thin layers are deposited (106) on the front side of the silicon wafer and the rear side of the silicon wafer. The four stepped indium tin oxide (ITO) thin layers includes first three-layer stack of thickness 10 nm, 5 nm, 10 nm and a subsequent fourth layer of thickness 55 nm. A stepped pressure variation is kept in the range of 8 mTorr to 3 mTorr during deposition of the four stepped ITO thin layers.
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