MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202641094154 A) filed by Presidency University on August 04, 2026, for System And Method For Implementing Smart Clock Gating In An Arithmetic Logic Unit (alu).
Inventor includes Aruna M.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: ABSTRACT System and Method for Implementing Smart Clock Gating in an Arithmetic Logic Unit (ALU) The present invention relates to a system and method for implementing intelligent clock gating in an arithmetic logic unit (ALU) for reducing dynamic power consumption in digital systems. The system comprises an input module (101) configured to receive input operands, an opcode input module (102) configured to receive a 3-bit opcode, and a plurality of functional modules (103) comprising arithmetic and logical operation units. A control unit (104) interprets the opcode and selectively activates a corresponding functional module through a clock gating logic unit (105). A gated clock generation circuit (106) generates a gated clock signal based on opcode selection and input activity of operands A and B. A multiplexer module (107) selects an output corresponding to the selected operation, and an output register (108) stores the ALU result using the gated clock signal. The invention minimizes unnecessary switching activity in inactive modules, thereby significantly reducing dynamic power consumption in FPGA-based and embedded digital systems.
Disclaimer: Curated by HT Syndication.
