MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202631085015 A) filed by Brainware University on July 10, 2026, for System And Method For Memory-Optimized Post-Quantum Cryptographic Execution In Edge Nodes.
Inventors include Mr. Susmit Chakraborty; Dr. Qaim Mehdi Rizvi; Mr. Dipanjan Guha Chowdhury; Mr. Pallab Paul; and Mr. Indrasish Das.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: The present disclosure relates to a system and method for memory-optimized post-quantum cryptographic execution in resource-constrained edge nodes. A memory- optimized post-quantum cryptographic edge apparatus (100) is deployed within a resource-constrained edge node (128) and comprises a microcontroller unit (102), a volatile memory module (104), an arithmetic execution unit (106), and a post-quantum cryptographic execution controller (108). The controller (108) includes an operand classifier (110), a compact operand-descriptor generator (112), a dynamic memory-window manager (114), an operand-liveness tracker (116), a leakage- controlled arithmetic scheduler (118), and a memory-fault guard (120). Polynomial operand data (126) is classified before dense materialization, and a compact operand-descriptor structure (124) guides allocation of an active memory window (122) within the volatile memory module (104). The execution pipeline (200) enables segmented operand materialization, buffer reuse, leakage-controlled arithmetic execution, and memory-threshold monitoring while preserving cryptographic output correctness.
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