MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202541068164 A) filed by International Institute Of Information Technology, Hyderabad on July 17, 2025, for System And Method For Stabilizing Clock Signal Frequency And Duty Cycle In Clock Generation Circuits.
Inventors include Vellanki Venkata Sundara Raghava Chetan Krishna; Busam Karthikeya; and Abhishek Srivastava.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: A system for generating clock signal using area and power-efficient PVT-compensated differential ring oscillator is provided. The system 100 includes temperature- compensated reference current source 102, process trimming circuit 104, current mirror circuit 106, CTAT resistor 108, voltage reference 114, low dropout regulator 112, and differential ring oscillator 110. The temperature-compensated reference current source 102 generates reference current, which is digitally trimmed by process trimming circuit to correct for process variation. The resulting process-trimmed current is mirrored by the current mirror circuit 106 and flow into both oscillator 110 and the CTAT resistor 108 where temperature-dependent degeneration is introduced. These current paths combine to form compensated bias current. Simultaneously, the voltage reference generator generates voltage reference 114 and LDO regulator 112 produces regulated supply voltage based on voltage reference. The oscillator 110 receives both regulated supply voltage and compensated bias current to generate frequency-stable clock signal with minimal PVT variation. FIG. 1
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