MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202611110329 A) filed by Ms. Bhavana Bhimineni on September 14, 2026, for System And Method For Timing And Power Optimization Of An Integrated Circuit Using Useful Clock Skew And Multi-Threshold-Voltage Cell Optimization.
Inventor includes Ms. Bhavana Bhimineni.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: A computer-implemented system and method are disclosed for coordinated timing and power optimization of an integrated circuit using useful clock skew and multi- threshold-voltage cell optimization. Design data is analyzed to determine timing-path criticalities, cell sensitivities, clock-endpoint sensitivities, leakage contributions, and admissible useful-skew intervals constrained by setup, hold, clock, and guard-band requirements. Functionally equivalent threshold-voltage cell substitutions and clock-skew adjustments are represented as coupled optimization actions and evaluated using a composite objective including timing benefit, leakage cost, electrical penalty, skew consumption, and multi-corner robustness. Selected actions are transactionally applied to a shadow design, incrementally verified against timing and electrical constraints, and selectively committed or rolled back according to realized benefit and risk. Residual timing deficits can be relieved by lower-threshold- voltage substitutions when skew is constrained, while recovered margin can be converted into leakage savings by higher-threshold-voltage substitutions. The process iterates until a convergence criterion is met and outputs optimized cell assignments, clock-arrival targets, and implementation instructions. Accompanied Drawing [FIGS. 1-2].
Disclaimer: Curated by HT Syndication.
