MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202641088646 A) filed by Dr. S. A. Arunmozhi; Mrs. V. Ramya; Mrs. J. Eindhumathy; Dr. B. Suganthi; Mr. G. Raja; Mrs. A. Sharan Jasmine; Mrs. U. Vidhya; and Dr. T. Jayakumar on July 21, 2026, for Ultra Low-Power Approximate Multiplier Architecture For Edge Ai Applications.
Inventors include Dr. S. A. Arunmozhi; Mrs. V. Ramya; Mrs. J. Eindhumathy; Dr. B. Suganthi; Mr. G. Raja; Mrs. A. Sharan Jasmine; Mrs. U. Vidhya; and Dr. T. Jayakumar.
The application for the patent was published on July 31, 2026, under issue no. 31/2026.
Abstract: TITLE: ULTRA LOW-POWER APPROXIMATE MULTIPLIER ARCHITECTURE FOR EDGE AI APPLICATIONS ABSTRACT The present invention relates to an ultra-low-power approximate multiplier architecture for Edge Artificial Intelligence applications. The proposed architecture comprises an input data buffer, operand preprocessing unit, approximation controller, approximate partial product generator, compressor reduction network, approximate carry propagation adder, power management unit, error monitoring module, output register, and Edge Al interface. The architecture dynamically selects approximation levels based on workload characteristics to minimize switching activity, silicon area, propagation delay, and power consumption while maintaining acceptable computational accuracy. Approximate compressor circuits and hybrid carry propagation significantly reduce hardware complexity and improve energy efficiency. Adaptive power management techniques including clock gating, operand isolation and voltage scaling further reduce energy consumption. The architecture is suitable for neural network accelerators, IoT processors, embedded Al devices, wearable electronics, and battery-powered systems requiring efficient multiply-intensive computations. E
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