MUMBAI, India, June 22 -- Intellectual Property India has published a patent application (202641036981 A) filed by Indian Institute Of Technology Dharwad on March 26, 2026, for Variable Oversampling Delta-Sigma Analog-To-Digital Converter And Operating Method Thereof.
Inventors include Pavan Kumar Km; and Prof. Naveen Kadayinti.
The application for the patent was published on June 12, 2026, under issue no. 24/2026.
Abstract: Disclosed is a variable oversampling rate delta-sigma analog-to-digital converter (ADC) (100) incorporating an LSB-first successive approximation register (SAR) (108a) as quantizer. The ADC 100 receives an analog input signal, generates an error signal using a summation node (102), and processes the error signal through a delta-sigma loop filter (104). The filtered signal is quantized using an LSB-first SAR ADC that begins each conversion from the digital output of the previous sample, thereby reducing the Initial State to Final State distance and enabling faster convergence. The conversion-end detection process monitors SAR bit-update activity and generates a non-uniform sampling-clock signal immediately upon conversion completion. This event-driven sampling eliminates idle time and allows consecutive samples to be captured at reduced time intervals, thereby increasing the effective oversampling ratio without increasing the control-clock frequency. The converter 100 provides improved conversion efficiency, enhanced noise shaping, and superior signal-to-noise performance in mixed-signal applications. Figure 1B will be the reference.
Disclaimer: Curated by HT Syndication.
